This invention relates in general to active matrix liquid crystal displays and in particular, to an active matrix liquid crystal display having light blocking, pixel enhancement, and photocurrent reduction features.
U.S. Pat. No. 3,862,360 issued to Dill et. al., describes one construction of an active matrix liquid crystal display ("AMLCD"). The AMLCD is formed by confining a thin layer of liquid crystal material between two plates. One plate is a glass (also referred to herein as "front plate"), which has one large transparent electrode formed on a surface adjacent to the confined liquid crystal material. The other plate, is a processed silicon substrate (also referred to herein as "back plate"), which has a plurality of reflective electrodes formed on a surface adjacent to the confined liquid crystal material.
The plurality of reflective electrodes define a plurality of pixels organized in a matrix array of rows and columns. To activate a pixel in the AMLCD, appropriate voltages are applied to a reflective electrode uniquely associated with that pixel and the front plate electrode. By applying such voltages to the reflective electrode and the front plate electrode, the molecular alignment of the liquid crystal material sandwiched between the two electrodes is altered. Depending upon the type of liquid crystal material being used, the material then acts as either a light valve or a light scattering medium to incident light entering through the front plate, passing through the liquid crystal material, and then being reflected back through the liquid crystal material and the front plate by the reflective electrode. For a general discussion on the structure and operation of such active matrix liquid crystal displays, see, e.g., Kaneko, E., LIQUID CRYSTAL TV DISPLAYS, KTK Scientific Publishers, Tokyo, 1987.
FIG. 1 illustrates an enlarged view of a portion of a front plate of an active matrix liquid crystal display (looking from the direction of entering incident light). Through the glass plate and its transparent electrode, the reflective electrodes (e.g., 11, 12, 21 and 22) can be seen on a silicon substrate 30. In laying out the reflective electrodes (e.g., 11, 12, 21 and 22) in an array of rows and columns on the silicon substrate 30, two key dimensions are the pixel pitch "PP" and the gap width "GW", as measured between adjacent reflective electrodes (e.g., 11 and 12).
Not shown in FIG. 1, but formed beneath each of the reflective electrodes (e.g., 11, 12, 21 and 22) is a field effect transistor ("FET") and a storage capacitor. The FET and storage capacitor associated with each reflective electrode, act together as an elemental sample and hold circuit for "sampling" a display signal transmitted to the source region of the FET through a signal electrode bus (also referred to herein as a "display signal bus") under the control of a row scanning signal transmitted to the gate electrode of the FET through a scanning electrode bus (also referred to herein as "row bus" or "gate bus"), and "holding" the voltage level of the display signal in the storage capacitor which is connected to the drain region of the FET, for the reflective electrode which is also connected to the drain region of the FET.
Gaps (e.g., 14) are required between each pair of adjacent reflective electrodes (e.g., 11 and 12) in order to electrically isolate the pair from each other. It is well known that for optimal viewing characteristics, the gap width "GW" should be minimalized and the smaller the ratio of the gap width "GW" to the pixel pitch "PP" the better. This is because the liquid crystal material over the gap areas is not controlled by the reflective electrodes and as a consequence, noticeable lines may appear on the display surface along these gap areas when the ratio of the gap width "GW" to the pixel pitch "PP" becomes too large.
Due to design and/or manufacturability limitations, each metallization process has a minimum gap width "GW" associated with that process. Because of this minimum gap width "GW" limitation, the gap width "GW" cannot continue to shrink proportionally with the pixel pitch "PP", as the pixel pitch "PP" gets smaller and smaller. Consequently, as the ratio of the gap width "GW" to the pixel pitch "PP" starts to increase, eventually, the ratio can become visually objectionable.
For example, in one metallization process, the minimum gap width "GW" might be 3.0 .mu.m. Using this minimum gap width, when the pixel pitch is 300.0 .mu.m, the gap width to pixel pitch ratio is only 1%, which makes the gap hardly noticeable visually. However, if the pixel pitch shrinks to 30.0 .mu.m, then the gap width to pixel pitch ratio becomes 10%, which may make the gap objectionable visually.
Another problem created by large gap widths is that when incident light passes through the gaps (e.g., 14), photons of light strike the silicon substrate 30 and generate electrons and holes that can affect the proper operation of the FETs and storage capacitors associated with each of the reflective electrodes (e.g., 11, 12, 21 and 22). A number of approaches have been developed in the past to counteract the effects of this phenomena.
For example, U.S. Pat. No. 4,103,297 issued to McGreivy et. al., describes a method of heavily doping the processed surface of a silicon substrate to desensitize the surface against incident light. The method requires additional processing steps over those conventionally required to form an AMLCD. Briefly stated, the extra steps comprise the steps of masking the surface with a layer of photoresist so as to expose all but the areas in which the FETs will be formed, ion implanting the exposed portions, then removing the mask. Such additional steps, however, objectionably add to the cost of fabricating an AMLCD of the type described.
U.S. Pat. Nos. 4,239,346 and 4,602,850 issued to Lloyd and DeBenedetti, respectively, both describe forming a continuous sheet of metallization to shield the substrate from incident light. In both approaches, the continuous sheet of metallization is formed beneath the reflective electrodes of the AMLCD and above the silicon substrate of the AMLCD, so as to shield the substrate from incident light passing through the gaps between the reflective electrodes. To provide electrical connections to the reflective electrodes, an array of holes conforming to the array of reflective electrodes is formed in the continuous sheet of metallization such that at least one hole is made directly beneath each reflective electrode. Connections are then formed through each of the holes which connect each of the reflective electrodes to their respective drive circuitry on the silicon substrate. Lloyd thereupon suggests using its continuous sheet of metallization as a common ground plate for the storage capacitors associated with each of its reflective electrodes, and DeBenedetti suggests using its continuous sheet of metallization as a third electrode to bias the liquid crystal for faster response times when voltages are selectively applied to the individual reflective electrodes.
One undesirable aspect of the Lloyd approach is that the signal electrode buses which transmit display signals to each of the FETs of the reflective electrodes, are not formed of metal. In Lloyd, the signal electrode buses comprise parallel diffusion channels formed in the silicon substrate. Since these diffusion channels have considerably higher resistance-capacitance characteristics than metal, they form far slower transmission paths for the display signals. As a consequence, the refresh rate to update a frame of the AMLCD must be accordingly slower.
Although it is not known what the signal electrode buses are formed of in DeBenedetti, it is believed that they are most likely formed of parallel polysilicon strips on the surface of the silicon substrate. Since these polysilicon strips, like the diffusion channels of Lloyd, have considerably higher resistance-capacitance characteristics than metal, they form far slower transmission paths for the display signals and as a consequence, the refresh rate to update a frame of the AMLCD must be accordingly slower.
One technique for forming metallized signal electrode buses which is compatible with forming a continuous sheet of metallization as a light shield, is to form the signal electrode buses in a third metallization layer wherein a first metallization layer is used for the continuous sheet of metallization used as the light shield, and a second metallization layer is used for the reflective electrodes. A second technique of forming metallized signal electrode buses is to form the signal electrode buses in the same layer as the reflective electrodes. The advantage of this second technique over the first technique is that only two layers of metallization need be formed. Since the continuous sheet of metallization used as a light shield is continuous, the signal electrode buses cannot be formed in the same metallization layer as the continuous sheet of metallization.
Both of these techniques for forming metallized signal electrode buses are undesirable, however. The problem with the first approach is that a third metallization layer would substantially and objectionably add to the cost of fabricating an AMLCD of the type described, and the problem with the second approach is that forming the signal electrode bus on the same layer as the reflective electrodes would increase the gap width size between adjacent reflective electrodes and consequently, deteriorate the AMLCD's visual characteristics.